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Analog Devices

Digital Design Engineer

Interview Date

April 2015 (Note: This is an older experience but provides detailed insights)

Result

Selected (implied by sharing detailed experience)

Difficulty

Written test questions were described as "a little

Rounds

Written test, followed by 2 interview rounds (Round 1: purely technical; Round 2: technical + HR).

Drive Type

On-Campus

Topics asked

Analog (current mirrors)Digital (FSMtimingdigital timingmultiplexersmetastability)C programminghardware design questions (non-repeating number in arraycounting ones in array).

Detailed experience

Role: Digital Design Engineer

College: Not Specified (Masters, VLSI and sequencing systems branches)

Interview Date: April 2015 (Note: This is an older experience but provides detailed insights)

Interview Type: On-Campus

Result: Selected (implied by sharing detailed experience)

Difficulty: Written test questions were described as "a little bit tricky," and time management was an issue during the exam.

Rounds: Written test, followed by 2 interview rounds (Round 1: purely technical; Round 2: technical + HR).

Topics Asked: Analog (current mirrors), Digital (FSM, timing, digital timing, multiplexers, metastability), C programming, hardware design questions (non-repeating number in array, counting ones in array).

Experience:

This on-campus recruitment process for a Digital Design Engineer at Analog Devices (for Masters students in VLSI and sequencing systems) began with a written test, followed by two interview rounds.

Written Test: This was a pen-and-paper subjective test lasting approximately 1.5 to 2 hours, consisting of 10 subjective questions and 4 MCQs. The test covered both analog and digital topics, with a heavier concentration on digital. Analog questions included current mirrors. Digital questions involved Finite State Machines (FSM) and timing, with specific emphasis on digital timing, which was considered tricky. One C programming question was based on command line arguments.

Round 1 (Purely Technical): This round focused heavily on the candidate's approach and correction of mistakes. Interviewers revisited questions from the written test where the candidate might have struggled. Specific questions included:

  • Implementing "alternating negative edges" FSM using a single flip-flop and combinational circuit.
  • A C programming question.
  • Designing hardware (using comparators) to find the non-repeating number in an array.
  • Designing hardware (using full adders) to count the number of ones in an array.
  • Questions on multiplexers, specifically how to avoid glitching in high-frequency applications.

Round 2 (Technical + HR): The second round had both technical and HR components.

  • Technical: A key question involved how to interface two systems operating at different frequencies and phases, with interviewers expecting an answer related to metastability and methods to avoid it, such as using a single flip-flop in front of a system.
  • HR: Standard HR questions were asked, including those about location preferences, family background, and reasons for not pursuing a PhD. The candidate was also given an opportunity to ask questions, such as about the job profile.

Posted on - 12 Nov 2025
Analog Devices Interview Experience - Digital Design Engineer | OAHelper