Analog Devices

Role: Design Verification Engineer

College: Not Specified

Interview Date: September 2023

Interview Type: Full-Time

Result: Selected (implied by sharing preparation strategy)

Difficulty: Not Specified

Rounds: 2 technical rounds after resume shortlisting.

Topics Asked: Projects (I2C, SPI protocols, FSM, Verilog, SV, UVM), handshaking, UVM environment configuration, assertions (for FIFO), Verilog coding (FSM), test cases.

Experience:

The interview process for a Design Verification Engineer role at Analog Devices involved two technical rounds following an initial resume shortlisting.

Round 1: This round primarily focused on the candidate's projects. Questions were asked about projects involving the I2C protocol, including its FSM states, Verilog code, and verification using SystemVerilog (SV) and UVM. The interviewer also inquired about handshaking mechanisms, how to configure different classes of the UVM environment, and writing assertions for verification, specifically for a FIFO.

Round 2: In the second technical round, the candidate was given a Verilog question on a finite state machine and asked to write the corresponding Verilog code. Questions also covered test cases for projects, such as an SPI protocol communicating with memory. Further questions on UVM included making a UV agent active and connecting the sequencer and driver, requiring the candidate to write code for these. Detailed questions about the SPI protocol's interface signals and state machine were also part of this round.