Cadence

Role: Analog Design Engineer (Intern)

College: Tier-I College

Interview Date: February 2024

Interview Type: Internship

Result: Not Specified (implies potential for PPO, as conversion rate is high)

Difficulty: Not Specified (implied Medium to Hard, "quite exhausting")

Rounds: 2 Rounds

Topics Asked: CMOS, Analog Circuits, VLSI Design, Process Corners, Post-Silicon Validation, RC Networks, Projects

Experience:

This interview experience is for an Analog Design Engineer Intern profile for a Tier-I college student, conducted in February 2024. The interview was virtual (web meet) and consisted of two rounds. The stipend offered was ₹45,000 monthly, and the location was Bangalore.

Round 1: Taken by a team member.

• The interviewer asked the student to open Paint to draw circuits and graphs.
• Draw a CMOS inverter and its VTC curve.
• Project-based questions (took 25-30 minutes).
• What are various process corners?
• What happens in post-silicon validation?
• Two basic questions from RC networks, asking about output and output nodes.

Round 2 (Manager - quite exhausting, 2.5 hours): Taken by the manager who leads the team. The interviewer would "grind" each question, providing hints if the candidate was stuck, and expecting a complete answer.

• Detailed questions related to the candidate's projects, including design choices and challenges.
• Advanced questions on CMOS design, device physics, and analog circuit analysis.
• Questions on timing analysis, power consumption, and layout considerations in VLSI.

Overall Experience: The interviewer in the second round was very thorough, not leaving any question unanswered and pushing the candidate to the very end of each problem. Cadence is noted for having a high conversion rate (90-95%) for interns to full-time employees.