Problem Statement

\n Multi-Core Cache Simulation \n \n \n You are tasked with simulating a multi-core system with N cores, where each core has its own L1 cache and there is a shared L2 cache across all cores. The system employs Least Recently Used (LRU) eviction policies for both L1 and L2 caches. There are M single-threaded processes, each identified by a unique Process ID (pid). These processes can be scheduled to run on any of the N cores in the system. \n\n Cache Behavior Rules: \n \n When a process is scheduled on a core, all the writes always go to L1 cache on that core. If the L1 cache is full, then the least recently used entry is evicted from L1 cache and added to L2 cache to accommodate the new entry. The system should also handle updates on an existing key. \n For reads, the system first checks the L1 cache on the core where the process is running, if not found returns from there else checks in L2 cache. Entries are not moved from L2 to L1 cache on a read. \n \n\n Process Migration: \n Proces